Non-volatile memory registers are commonly used in memory device chips to implement redundancy. In such applications, address configurations corresponding to defective memory elements in the memory array of the memory device are stored in said non-volatile registers during the in-factory device testing, so that the defective memory elements can be replaced by redundant memory elements. In this way the manufacturing process yield is greatly improved. The memory registers must be non-volatile, since they must retain the information stored therein even in absence of the power supply, and not accessible to the end user. Depending on the particular kind of memory device, and on the manufacturing process, fuses or electrically programmable MOS transistors may be utilized as non-volatile memory elements for the memory registers.
In general, redundancy provides for the existence of both rows and columns of redundant memory elements; each redundant row or column has an associated non-volatile register. A defective memory element in the memory matrix can be replaced by a redundant memory element by substituting either the matrix row or matrix column to which it belongs with a redundant row or column, respectively; this requires that the defective row or column address is stored during testing in a non-volatile register, which, in consequence, must be made up of a number of cells equal to the number of bits in the row or column address bus.
During the memory device operation, each non-volatile memory register performs a comparison between the address configuration stored in it and the address currently supplied to the memory device and, if a matching occurs, the selection of the defective row or column is inhibited and in substitution the selection of the redundant row or column is enabled.
According to a known technique of implementing redundancy in a Flash EEPROM device, each register cell comprises two programmable non-volatile memory elements, represented by two electrically erasable and programmable MOS transistors, connected to respective load transistors in latch configuration. The register cell further comprises a program load circuit comprising two pairs of selection transistors, the transistors in each pair being connected in series between a high voltage supply and a respective programmable MOS transistor. A first transistor in each pair is controlled by a first signal, supplied in common to all the cells of all the non-volatile memory registers, which is normally at the ground level, but when during the device testing a defective memory element is found is raised to the high voltage supply value to enable the programming of the programmable MOS transistors of the non-volatile registers. A second transistor in each pair is instead controlled by a selection signal which is used to select one particular non-volatile memory register among all those available, so that only the programmable MOS transistors of the selected memory register are programmed to store a particular address configuration corresponding to a defective matrix row or column. The control gates of the programmable MOS transistors in each register cell are controlled by two signals, one of which is the logical complement of the other, which during programming are connected either to ground or to the high voltage supply depending on the logical state of the bit of the address configuration which must be stored in the register cell.
In other words, when the logical state of an address bit is to be memorized into the register cell, each programmable MOS transistor is connected to a high voltage supply through selection transistors, and the datum to be programmed is translated into a voltage applied to the control gate of the programmable MOS transistor: if the datum is a logical "0", the control gate potential is raised to, let's say, 12 V, while if the datum is a logical "1", the control gate potential is kept to the ground level.
A register cell architecture such as that described above has some disadvantages: first of all it is necessary to supply said first signal, connected to the output of a ground/high-voltage switch, to all the cells of all the non-volatile memory registers; secondly, a number of different selection signals corresponding to the number of non-volatile memory registers must be generated, so that in each register a different address configuration can be programmed; thirdly, it is necessary to generate two complementary signals for each register cell to drive the control gates of the programmable MOS transistors. Furthermore, to prevent the programming current of the programmable MOS transistors from being reduced, the transistors in the program load circuit must be highly conductive, and occupy a significant area. Finally, it would be desirable to reduce the number of transistors of each program load circuit.